Proper formatting makes code easier to read and understand.
Please make a backup before you replace your code!
Report bugs if your code is not properly formatted, please provide sample code which causes the failure
output sample
LIBRARY IEEE; -- declare the library
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
(All reserved words are in capital)
(All indents are in the right place)
---------------------------------------------------------------
ENTITY example IS
PORT (
rst : IN std_logic;
clk : IN std_logic;
example_of_long_words : OUT std_logic_vector(3 DOWNTO 0)
(Align signs in PORT() aligns these colons)
);
END example;
ARCHITECTURE EXA OF example IS
ALIAS slv IS std_logic_vector;
SUBTYPE bit4 IS slv(3 DOWNTO 0); (Check ALIAS replaces all "std_logic_vector" with "slv")
BEGIN
REPORT "Hello World"; (Remove REPORT)
stages : PROCESS (rst, clk)
BEGIN
IF (rst = '0') THEN
CASE bit4 IS
WHEN "0000" => bit4 <= "0001";
WHEN "0001" => bit4 <= "0100";
WHEN "0010" => bit4 <= "0010";
WHEN "0100" => bit4 <= "0000";
WHEN OTHERS =>
REPORT "Are there any more cases?"; (Remove REPORT)
END CASE;
ELSIF (clk'event AND clk = '1') THEN
IF (bit4 = '0111') THEN
bit4 <= "0000";
ELSE
bit4 <= "1111";
END IF;
-- Sample comments 1;
-- Sample comments 2; (Remove comments)
END IF;
END PROCESS;
END EXA;